CacheStart (U6/10) -- deglitched by U31b Begin Cache Memory Operation Clear A Sel (U5/4) Clear U12b -- Disable Shift Register A data buffers Clear B Sel (U2/8) Clear U21b -- Disable Shift Register B Data Buffers Clear CRC to WD (U5/1) Clear U34b -- Inhibit output of CRC shift register to write data encoder Clear CtrlOut (U4/2) -- also ClrCmd Clear U20b -- Deassert Drive Control strobe ClrCmd : Clear cable buffer U9a -- inhibit command bits to drive Outbus Clear CycSel (U1/5) Clear U23a -- Select short cycle counts Set U28a -- Enable shift register serial output to write data encoder Clear D to SR (U2/7) Clear U19a -- Disable buffers from cache to selected shift register(s) Clear Data Path (U1/0) Clear U16a -- Inhibit Read Data to CRC register Clear U16b -- Disable Cycle Counter clock Clear U17a -- Clear spare instruction output Clear U27a -- Hold 'Read 1 found' Flip-flop (Address Control U13b) reset Clear U27b -- Inhibit CRC register clock Clear MClkSel (U3/3) Clear U18b -- Select crystal clock Clear SR A En (U3/8) Clear U20a -- Deassert Shift Register A parallel load enable Clear U23b -- Inhibit Shift Register A clock Clear U24b -- Disable buffers from address register to shift register Clear SR A Sout En (U6/5) Clear U22b -- Inhibit Shift Register A serial output (to CRC and write encoder) Clear SR B Load (U1/8) Clear U17b -- Inhibit Shift Register B clock Set U19b -- Deassert Shift Register B parallel load enable Clear SR to D (U5/6) Clear U18a -- Disable buffers from selected shift register to cache Clr SIn En (U2/0) Clear U17b -- Inhibit Shift Register B clock Clear U12a -- Inhibit serial input to shift registers (forced high) Clear U29b -- Deassert instruction shift register clock Clr SR A (U5/14) -- deglitched by U31f Clear shift register A ClrCRC (U3/13) -- deglitched by U30f Clear CRC chift register ClrCacheAddr (U1/9) -- deglitched by U30a Clear Cache memory address counter ClrSktst (U4/10) -- deglitched by U30d Clear U21a -- Deassert Calculator Ia signal Clear U24a -- Calculator error flip-flop Clear U34a -- Deassert Calcualtor Ib signal Clear Data Transfer U22a -- Inhibit seek error test Clear Cycle counter (Address Control PCB) LdAddr (U1/10) -- deglitched by U29a Strobe calculator data outputs to address register (Data Transfer PCB) Set A Sel(a) (U5/12) ] ORed by U11d Set A Sel(b) (U4/4) ] Set U12b -- Enable Shift Register A data buffers Set Addr to SR (U6/8) Set U24b -- Enable buffers from address register to selected shift register(s) Set B Sel(a) (U5/8) ] Ored by U11b Set B Sel(b) (U6/2) ] Set U21b -- Enable Shift Register B data buffers Set CCLk En (U4/8) Set U16b -- Enable cycle counter clock Set CRC Clock En (U2/4) Set U27b -- Enable CRC register clock Set CRC to WD (U3/10) Clear U28a -- Inhibit shift register serial output to write data encoder Clear U28b -- Inhibit shift register serial output to CRC register Set U34b -- Enable CRC register output to write data encoder Set Calc Ia (U5/9) Set U21a -- Assert Calcualtor Ia signal Set Calc Ib (U4/12) Set U34a -- Assert Calcualtor Ib signal Set Ctrl Out (U2/10) Set U20b -- Assert drive control strobe Set CycSel (U5/2) Set U17a -- Assert spare instruction output Set U23a -- Select long cycle counts Set D to SR (U4/1) Set U19a -- Enable buffers from cache to selected shift register(s) Set Head (U2/11) -- Deglitched by U30c Set Data Transfer U22a -- enable seek error check Assert drive head select strobe Set Inst SR Clock (U2/1) Set U29b -- Assert instruction shift register clock Set MClkSel (U1/7) Set U18b -- Select PLL clock Set Rd Sync (U5/0) Set U27a -- Remove reset from 'Read 1 found' flip-flop Set SIn En (U4/0) Set U12a -- Enable serial input to selected shift register(s) Set SOUT to CRC (U1/4) Set U28b -- Enable shift register serial output to CRC register Set SR A En (U3/4) Set U23b -- Enable clock to shift register A Set SR A Load (U1/2) Set U20a -- Assert shift register A parallel load enable Set SR A SOut En (U4/9) Clear U22a -- Disable shift register B serial output Set U22b -- Enable shift register A serial output Set SR B En (U1/1) Set U17b -- Enable clock to shift register B Set SR B Load (U2/2) Clear U19b -- Assert shift register B parallel load enable Set SR B SOut En (U5/5) Set U22a -- Enable shift register B serial output Set SR to D (U1/6) Set U18a -- Enable buffers from cache to selected shift register Set Sin to CRC (U2/6) Set U16a -- Enable read data to CRC register SetCmd (U3/6) -- Deglitched by U30e Set Cable buffer U9a -- Enable command bits to drive Outbus Clear Cable buffer U11a -- Disable cylinder addres to drive Outbus Clear Cable buffer U11b -- Disable head address to drive Outbus SetCyl (U6/6) -- Deglitched by U31a Assert drive cylinder select strobe SetCylEn (U4/5) -- Deglitched by U31d Set Cable buffer U11a -- Enable cylinder address to drive Outbus Clear Cable buffer U11b -- Disable head address to drive Outbus SetHdEn (U3/5) -- Deglitched by U31e Set Cable buffer U11b -- Enable head address to drive Outbus Stat (U6/14) -- Deglitched by U31c Assert Calculator status line Tr Off (U2/5) Set Data Transfer U22b -- Disable transfers and DrWr signal. Force Read Mode Tr On (U2/3) Clear Data Transfer U22b -- Enable transfer and selected Read/Write mode